Physical Architecture of Co-Packaged Optics
Co-Packaged Optics (CPO) represents a fundamental departure from traditional modular transceiver architectures. Rather than housing optical transceivers in separate line cards connected via electrical backplanes, CPO integrates photonic components directly alongside the switching silicon on a single substrate or within a tightly coupled multi-chip module. This integration dramatically reduces latency and power consumption, but introduces unprecedented complexity in signal synchronization.
The physical layout of a CPO switch consists of several interdependent layers. At the foundation lies the silicon photonics die, containing wavelength division multiplexing (WDM) components, photodiodes, and optical modulators. This die interfaces with the packet-switching ASIC, which performs forwarding decisions and queue management. Between these two components sits a critical optical-to-electronic (O/E) conversion layer that translates incoming photonic signals into electrical packets and vice versa.
Silicon Photonics Die Components
The silicon photonics die integrates multiple functional blocks into a single monolithic or heterogeneously integrated structure. Optical modulators (typically Mach-Zehnder interferometers) convert electrical control signals into optical intensity variations at specific wavelengths. These operate at extremely high speedsâmodern designs support 400 Gbps per wavelength through 16 parallel 25 Gbps lanes or equivalent multilevel modulation schemes.
Photodiode arrays detect incoming optical signals and convert them back to electrical current. These detectors are typically integrated with transimpedance amplifiers (TIAs) to achieve sufficient signal levels for downstream digital processing. The integration of TIA amplifiers directly on the photonics die is crucial because it minimizes parasitic capacitance and reduces jitter introduced by long electrical traces.
Wavelength-selective components such as arrayed waveguide gratings (AWGs) or microring resonators separate incoming WDM signals into individual wavelength channels. Each wavelength typically carries one or more data streams. For example, a 400 Gbps CPO port might use 8 wavelengths, each carrying 50 Gbps of traffic.
Signal Pathways and Data Flow
Understanding signal pathways is essential for diagnosing desynchronization issues. Consider a typical ingress path: an external optical fiber carries WDM-multiplexed data into the CPO module. This signal enters the photonics die where it is demultiplexed by wavelength. Each wavelength channel is directed to a dedicated photodiode-TIA pair, producing an electrical signal representing the original data stream.
These electrical signals then enter clock and data recovery (CDR) circuits, which extract timing information from the incoming signal and regenerate clean clock and data signals. This is a critical juncture: the CDR must lock to the remote transmitter's clock while operating independently from the local switching ASIC's clock domain. Modern CDRs achieve lock times of microseconds, but during transient periods, timing mismatches accumulate.
The recovered data and clock then pass into demultiplexing logic that converts high-speed serial data (e.g., 25 Gbps) into lower-speed parallel words (e.g., 64-bit words at ~400 MHz). These parallel words are buffered in small elastic buffers before entering the main packet buffer memory.
Egress Path and Timing Sensitivity
The egress path follows the reverse sequence. Packets stored in the switching ASIC's buffer are read out and serialized into high-speed electrical signals. These signals drive the optical modulators on the photonics die, which convert them into optical intensity variations. The modulated signal is then multiplexed with other wavelength channels and transmitted onto the external fiber.
The critical insight is that the ingress and egress paths operate on different clock domains. The incoming signal is locked to the remote transmitter's clock (recovered by the CDR), while the outgoing signal is driven by the local switching ASIC's clock. These clocks are nominally the same frequency (e.g., both 10 GHz) but have independent phase relationships and frequency stability characteristics. Even small frequency differences accumulate over time, causing buffers to overflow or underflow.
Real-World Layout Constraints
In practice, CPO switches are constrained by physical dimensions. A typical module measures 20mm Ă 15mm and contains the photonics die, switching ASIC, buffer memory, and power delivery circuits. The photonics die alone occupies only 3-4 mmÂČ but generates significant heat through optical modulation losses. This heat directly affects wavelength stability and clock jitterâa phenomenon explored in Sub-module 1.3.
The electrical connections between the photonics die and switching ASIC are implemented as micro-bumps or fine-pitch solder balls, introducing parasitic inductance and capacitance. These parasitics cause signal reflections and timing skew that varies with process corners, operating temperature, and voltage. This variation is a primary source of desynchronization that traditional network telemetry systems cannot detect because it occurs entirely within the CPO module.